1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems having at least one cache memory unit. The use of cache memory units can result in storage of a data signal group in a plurality of locations. Each copy of a data signal group stored throughout the data processing system must be equivalent. Otherwise procedures must be instituted to avoid inconsistent results that can arise from independent manipulation of the copies of a data signal group by the components of the data processing system.
2. Description of the Related Art
It is known in data processing systems having the possibility of multiple copies of a data signal group, such as can occur when cache memory units are used with associated data processing units, to provide that one copy of the data signal group is the master copy of the data signal group and any changes in the data signal group are immediately communicated to master copy. At the same time, other copies of the data signal group can be invalidated when any change in the data signal group is identified. The invalidation of the data signal group is typically performed by changing the state or logic level of stored control signals associated with each stored entry of the non-master data signal groups. The associated stored control signals are sometimes referred to as tag signals, however tag signals can also have other meanings in the computer art. Any access of the cache memory unit data signal group by the associated data processing unit can result in the appropriate control signal state being interrogated and a determination made as to the validity of the data group. If the data signal group is not valid, the signal group is unavailable to the associated data processing unit.
This procedure can suffer from several disadvantages. The most important disadvantage arises because many implementations of this procedure require that duplicate cache directories be associated with each data processing system so that entries of each cache memory unit are known and data signal groups stored in every cache memory unit can be identified. While the duplicate directories can limit the required bus activity, the duplicate cache directories must have a plurality of communication paths to update the related control signals when data signal groups are being altered. Thus, this technique of data signal group verification is complex and requires additional apparatus in its implementation.
Similarly, related procedures identify one data signal group, typically the main memory data signal group, as being the "correct" signal group. This procedure requires that when a data group is updated, it must be stored in the main memory and then extracted when a data processing unit requires the data signal group. The main memory access is typically longer than a cache memory access and an undesirable increase in system bus traffic can result from this procedure.
A need has therefore been felt for a data processing system with multiple cache memory units, that has reduced system bus activity while providing an efficient procedure for the indivivdual data processing units, associated with each cache memory unit, to acquire the preferred copy of a requested data signal groups.